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? 2005 microchip technology inc. ds21749f-page 1 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c device selection table features: ? low-power cmos technology ? org pin to select word size for ?46c? version ? 128 x 8-bit organization ?a? version devices (no org) ? 64 x 16-bit organization ?b? version devices (no org) ? self-timed erase/write cycles (including auto-erase) ? automatic eral before wral ? power-on/off data protection circuitry ? industry standard 3-wire serial i/o ? device status signal (ready/busy ) ? sequential read function ? 1,000,000 e/w cycles ? data retention > 200 years ? temperature ranges supported: pin function table description: the microchip technology inc. 93xx46a/b/c devices are 1k bit low-voltage serial electrically erasable proms (eeprom). word-selectable devices such as the 93aa46c, 93lc46c or 93c46c are dependent upon external logic levels driving the org pin to set word size. for dedicated 8-bit communication, the 93aa46a, 93lc46a or 93c46a devices are available, while the 93aa46b, 93lc46b and 93c46b devices provide dedicated 16-bit communication. advanced cmos technology makes these devices ideal for low power, nonvolatile memory applications. the entire 93xx series is available in standard packages includ- ing 8-lead pdip and soic, and advanced packaging including 8-lead msop, 6-lead sot-23, 8-lead 2x3 dfn and 8-lead tssop. pb-free (pure matte sn) finish is also available. part number v cc range org pin word size temp ranges packages 93aa46a 1.8-5.5 no 8-bit i p, sn, st, ms, ot, mc 93aa46b 1.8-5-5 no 16-bit i p, sn, st, ms, ot, mc 93lc46a 2.5-5.5 no 8-bit i, e p, sn, st, ms, ot, mc 93lc46b 2.5-5.5 no 16-bit i, e p, sn, st, ms, ot, mc 93c46a 4.5-5.5 no 8-bit i, e p, sn, st, ms, ot, mc 93c46b 4.5-5.5 no 16-bit i, e p, sn, st, ms, ot, mc 93aa46c 1.8-5.5 yes 8 or 16-bit i p, sn, st, ms, mc 93lc46c 2.5-5.5 yes 8 or 16-bit i, e p, sn, st, ms, mc 93c46c 4.5-5.5 yes 8 or 16-bit i, e p, sn, st, ms, mc - industrial (i) -40c to +85c - automotive (e) -40c to +125c name function cs chip select clk serial data clock di serial data input do serial data output v ss ground nc no internal connection org memory configuration v cc power supply 1k microwire compatible serial eeprom
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 2 ? 2005 microchip technology inc. package types (not to scale) cs clk di do 1 2 3 4 8 7 6 5 v cc nc org * v ss pdip/soic (p, sn) cs clk di do 1 2 3 4 8 7 6 5 v cc nc org* v ss rotated soic (ex: 93lc46bx) tssop/msop cs clk di do 1 2 3 4 8 7 6 5 v cc nc org* v ss (st, ms) sot-23 do v ss di 1 2 3 6 5 4 v cc cs clk (ot) * org pin is nc on a/b devices dfn cs clk di do nc org* v ss v cc 8 7 6 5 1 2 3 4
? 2005 microchip technology inc. ds21749f-page 3 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ..........................................................................................................-0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied......................................................................................... .......-40c to +125c esd protection on all pins ............................................................................................................................... ....................... 4kv table 1-1: dc characteristics ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. all parameters apply over the specified ranges unless otherwise noted. industrial (i): t a = -40c to +85c, v cc = +1.8v to +5.5v automotive (e): t a = -40c to +125c, v cc = +2.5v to +5.5v param. no. symbol parameter min typ max units conditions d1 v ih 1 v ih 2 high-level input voltage 2.0 0.7 v cc ? ? v cc +1 v cc +1 v v v cc 2.7v v cc < 2.7v d2 v il 1 v il 2 low-level input voltage -0.3 -0.3 ? ? 0.8 0.2 v cc v v v cc 2.7v v cc < 2.7v d3 v ol 1 v ol 2 low-level output voltage ? ? ? ? 0.4 0.2 v v i ol = 2.1 ma, v cc = 4.5v i ol = 100 a, v cc = 2.5v d4 v oh 1 v oh 2 high-level output voltage 2.4 v cc - 0.2 ? ? ? ? v v i oh = -400 a, v cc = 4.5v i oh = -100 a, v cc = 2.5v d5 i li input leakage current ? ? 1 av in = v ss or v cc d6 i lo output leakage current ? ? 1 av out = v ss or v cc d7 c in , c out pin capacitance (all inputs/outputs) ??7pfv in /v out = 0v (note 1) t a = 25c, f clk = 1 mhz d8 i cc write write current ? ? ? 500 2 ? ma a f clk = 3 mhz, v cc = 5.5v f clk = 2 mhz, v cc = 2.5v d9 i cc read read current ? ? ? ? ? 100 1 500 ? ma a a f clk = 3 mhz, v cc = 5.5v f clk = 2 mhz, v cc = 3.0v f clk = 2 mhz, v cc = 2.5v d10 i ccs standby current ? ? ? ? 1 5 a a i-temp e-temp clk = cs = 0v org = di = v ss or v cc (note 2) (n ote 3) d11 v por v cc voltage detect ? ? 1.5 3.8 ? ? v v (note 1) 93aa46a/b/c, 93lc46a/b/c 93c46a/b/c note 1: this parameter is periodically sampled and not 100% tested. 2: org pin not available on ?a? or ?b? versions. 3: ready/busy status must be cleared from do, see section 3.4 "data out (do)" .
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 4 ? 2005 microchip technology inc. table 1-2: ac characteristics all parameters apply over the specified ranges unless otherwise noted. industrial (i): t a = -40c to +85c, v cc = +1.8v to +5.5v automotive (e): t a = -40c to +125c, v cc = +2.5v to +5.5v param. no. symbol parameter min max units conditions a1 f clk clock frequency ? 3 2 1 mhz mhz mhz 4.5v v cc < 5.5v, 93xx46c only 2.5v v cc < 5.5v 1.8v v cc < 2.5v a2 t ckh clock high time 200 250 450 ?ns ns ns 4.5v v cc < 5.5v, 93xx46c only 2.5v v cc < 5.5v 1.8v v cc < 2.5v a3 t ckl clock low time 100 200 450 ?ns ns ns 4.5v v cc < 5.5v, 93xx46c only 2.5v v cc < 5.5v 1.8v v cc < 2.5v a4 t css chip select setup time 50 100 250 ?ns ns ns 4.5v v cc < 5.5v 2.5v v cc < 4.5v 1.8v v cc < 2.5v a5 t csh chip select hold time 0 ? ns 1.8v v cc < 5.5v a6 t csl chip select low time 250 ? ns 1.8v v cc < 5.5v a7 t dis data input setup time 50 100 250 ?ns4.5v v cc < 5.5v, 93xx46c only 2.5v v cc < 5.5v 1.8v v cc < 2.5v a8 t dih data input hold time 50 100 250 ?ns4.5v v cc < 5.5v, 93xx46c only 2.5v v cc < 5.5v 1.8v v cc < 2.5v a9 t pd data output delay time ? ? ? 200 250 400 ns 4.5v v cc < 5.5v, c l = 100 pf 2.5v v cc < 4.5v, c l = 100 pf 1.8v v cc < 2.5v, c l = 100 pf a10 t cz data output disable time ? ? 100 200 ns 4.5v v cc < 5.5v, (note 1) 1.8v v cc < 4.5v, (note 1) a11 t sv status valid time ? 200 300 500 ns 4.5v v cc < 5.5v, c l = 100 pf 2.5v v cc < 4.5v, c l = 100 pf 1.8v v cc < 2.5v, c l = 100 pf a12 t wc program cycle time ? 6 ms erase/write mode (aa and lc versions) a13 t wc ? 2 ms erase/write mode (93c versions) a14 t ec ? 6 ms eral mode, 4.5v v cc 5.5v a15 t wl ? 15 ms wral mode, 4.5v v cc 5.5v a16 ? endurance 1m ? cycles 25c, v cc = 5.0v, (note 2) note 1: this parameter is periodically sampled and not 100% tested. 2: this application is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which may be obtained from microchip?s web site at www.microchip.com.
? 2005 microchip technology inc. ds21749f-page 5 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c figure 1-1: synchronous data timing table 1-3: instruction set for x 16 organization (93xx46b or 93xx46c with org = 1) table 1-4: instruction set for x 8 organization (93xx46a or 93xx46c with org = 0) instruction sb opcode address data in data out req. clk cycles erase 1 11 a5 a4 a3 a2 a1 a0 ? (rdy/bsy )9 eral 1 00 10xxxx ? (rdy/bsy )9 ewds 1 00 00xxxx ? high-z 9 ewen 1 00 11xxxx ? high-z 9 read 1 10 a5 a4 a3 a2 a1 a0 ? d15 - d0 25 write 1 01 a5 a4 a3 a2 a1 a0 d15 - d0 (rdy/bsy )25 wral 1 00 01xxxx d15 - d0 (rdy/bsy )25 instruction sb opcode address data in data out req. clk cycles erase 1 11 a6 a5 a4 a3 a2 a1 a0 ? (rdy/bsy )10 eral 1 00 10xxxxx ? (rdy/bsy )10 ewds 1 00 00xxxxx ?high-z 10 ewen 1 00 11xxxxx ?high-z 10 read 1 10 a6 a5 a4 a3 a2 a1 a0 ? d7 - d0 18 write 1 01 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rdy/bsy )18 wral 1 00 01xxxxx d7 - d0 (rdy/bsy )18 cs v ih v il v ih v il v ih v il v oh v ol v oh v ol clk di do (read) do (program) t css t dis t ckh t ckl t dih t pd t csh t pd t cz status valid t sv t cz note: t sv is relative to cs.
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 6 ? 2005 microchip technology inc. 2.0 functional description when the org pin (93xx46c) is connected to v cc , the (x16) organization is selected. when it is connected to ground, the (x8) organization is selected. instruc- tions, addresses and write data are clocked into the di pin on the rising edge of the clock (clk). the do pin is normally held in a high-z state except when reading data from the device, or when checking the ready/ busy status during a programming operation. the ready/busy status can be verified during an erase/ write operation by polling the do pin; do low indicates that programming is still in progress, while do high indicates the device is ready. do will enter the high-z state on the falling edge of cs. 2.1 start condition the start bit is detected by the device if cs and di are both high with respect to the positive edge of clk for the first time. before a start condition is detected, cs, clk and di may change in any combination (except to that of a start condition), without resulting in any device operation (read, write, erase, ewen, ewds, eral or wral). as soon as cs is high, the device is no longer in standby mode. an instruction following a start condition will only be executed if the required opcode, address and data bits for any particular instruction are clocked in. 2.2 data in/data out (di/do) it is possible to connect the data in and data out pins together. however, with this configuration it is possible for a ?bus conflict? to occur during the ?dummy zero? that precedes the read operation, if a0 is a logic high level. under such a condition the voltage level seen at data out is undefined and will depend upon the relative impedances of data out and the signal source driving a0. the higher the current sourcing capability of a0, the higher the voltage at the data out pin. in order to limit this current, a resistor should be connected between di and do. 2.3 data protection all modes of operation are inhibited when v cc is below a typical voltage of 1.5v for '93aa' and '93lc' devices or 3.8v for '93c' devices. the ewen and ewds commands give additional protection against accidentally programming during normal operation. after power-up, the device is automatically in the ewds mode. therefore, an ewen instruction must be performed before the initial erase or write instruction can be executed. block diagram note: when preparing to transmit an instruction, either the clk or di signal levels must be at a logic low as cs is toggled active high. note: for added protection, an ewds command should be performed after every write operation and an external 10 k pull-down protection resistor should be added to the cs pin. memory array data register mode decode logic clock register address decoder address counter output buffer do di org* cs clk v cc v ss *org input is not available on a/b devices
? 2005 microchip technology inc. ds21749f-page 7 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 2.4 erase the erase instruction forces all data bits of the specified address to the logical ?1? state. cs is brought low following the loading of the last address bit. this falling edge of the cs pin initiates the self-timed programming cycle, except on ?93c? devices where the rising edge of clk before the last address bit initiates the write cycle. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). do at logical ? 0 ? indicates that programming is still in progress. do at logical ? 1 ? indicates that the register at the specified address has been erased and the device is ready for another instruction. figure 2-1: erase timing for 93aa and 93lc devices figure 2-2: erase timing for 93c devices note: after the erase cycle is complete, issuing a start bit and then taking cs low will clear the ready/busy status from do. cs clk di do t csl check status 111 a n a n -1 a n -2 ??? a0 t sv t cz b usy ready high-z t wc high-z cs clk di do t csl check status 111 a n a n -1 a n -2 ??? a0 t sv t cz b usy ready high-z t wc high-z
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 8 ? 2005 microchip technology inc. 2.5 erase all (eral) the erase all ( eral ) instruction will erase the entire memory array to the logical ? 1 ? state. the eral cycle is identical to the erase cycle, except for the different opcode. the eral cycle is completely self-timed and commences at the falling edge of the cs, except on ?93c? devices where the rising edge of clk before the last data bit initiates the write cycle. clocking of the clk pin is not necessary after the device has entered the eral cycle. the do pin indicates the ready/busy status of the device, if cs is brought high after a minimum of 250 ns low (t csl ). v cc must be 4.5v for proper operation of eral. figure 2-3: eral timing for 93aa and 93lc devices figure 2-4: eral timing for 93c devices note: after the eral command is complete, issuing a start bit and then taking cs low will clear the ready/busy status from do. cs clk di do t csl check status 100 10x ??? x t sv t cz busy ready high-z t ec high-z v cc must be 4.5v for proper operation of eral. cs clk di do t csl check status 100 10x ??? x t sv t cz busy ready high-z t ec high-z
? 2005 microchip technology inc. ds21749f-page 9 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 2.6 erase/write disable and enable (ewds/ewen) the 93xx46a/b/c powers up in the erase/write disable (ewds) state. all programming modes must be preceded by an erase/write enable ( ewen ) instruction. once the ewen instruction is executed, programming remains enabled until an ewds instruction is executed or vcc is removed from the device. to protect against accidental data disturbance, the ewds instruction can be used to disable all erase/write functions and should follow all programming operations. execution of a read instruction is independent of both the ewen and ewds instructions. figure 2-5: ewds timing figure 2-6: ewen timing 2.7 read the read instruction outputs the serial data of the addressed memory location on the do pin. a dummy zero bit precedes the 8-bit (if org pin is low or a-version devices) or 16-bit (if org pin is high or b-version devices) output string. the output data bits will toggle on the rising edge of the clk and are stable after the specified time delay (t pd ). sequential read is possible when cs is held high. the memory data will automatically cycle to the next register and output sequentially. figure 2-7: read timing cs clk di 10 000x ??? x t csl 1x cs clk di 00 1 1x t csl ??? cs clk di do 110 an ??? a0 high-z 0 dx ??? d0 dx ??? d0 ??? dx d0
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 10 ? 2005 microchip technology inc. 2.8 write the write instruction is followed by 8 bits (if org is low or a-version devices) or 16 bits (if org pin is high or b-version devices) of data which are written into the specified address. for 93aa46a/b/c and 93lc46a/b/c devices, after the last data bit is clocked into di, the falling edge of cs initiates the self-timed auto-erase and programming cycle. for 93c46a/b/c devices, the self- timed auto-erase and programming cycle is initiated by the rising edge of clk on the last data bit. the do pin indicates the ready/busy status of the device, if cs is brought high after a minimum of 250 ns low (t csl ). do at logical ? 0 ? indicates that programming is still in progress. do at logical ? 1 ? indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. figure 2-8: write timing for 93aa and 93lc devices figure 2-9: write timing for 93c devices note: after the write cycle is complete, issuing a start bit and then taking cs low will clear the ready/busy status from do. cs clk di do 1 0 1 an ??? a0 dx ??? d0 busy ready high-z high-z t wc t csl t cz t sv cs clk di do 1 0 1 an ??? a0 dx ??? d0 busy ready high-z high-z t wc t csl t cz t sv
? 2005 microchip technology inc. ds21749f-page 11 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 2.9 write all (wral) the write all ( wral ) instruction will write the entire memory array with the data specified in the command. for 93aa46a/b/c and 93lc46a/b/c devices, after the last data bit is clocked into di, the falling edge of cs initiates the self-timed auto-erase and programming cycle. for 93c46a/b/c devices, the self-timed auto- erase and programming cycle is initiated by the rising edge of clk on the last data bit. clocking of the clk pin is not necessary after the device has entered the wral cycle. the wral command does include an automatic eral cycle for the device. therefore, the wral instruction does not require an eral instruction, but the chip must be in the ewen status. the do pin indicates the ready/busy status of the device if cs is brought high after a minimum of 250 ns low (t csl ). v cc must be 4.5v for proper operation of wral. figure 2-10: wral timing for 93aa and 93lc devices figure 2-11: wral timing for 93c devices note: after the write all cycle is complete, issuing a start bit and then taking cs low will clear the ready/busy status from do. cs clk di do h igh -z 1 0 0 01 x ??? x dx ??? d0 high-z busy ready t wl v cc must be 4.5v for proper operation of wral. t csl t sv t cz cs clk di do h igh -z 1 0 0 01 x ??? x dx ??? d0 high-z busy ready t wl t csl t sv t cz
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 12 ? 2005 microchip technology inc. 3.0 pin descriptions table 3-1: pin descriptions 3.1 chip select (cs) a high level selects the device; a low level deselects the device and forces it into standby mode. however, a programming cycle which is already in progress will be completed, regardless of the chip select (cs) input signal. if cs is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. cs must be low for 250 ns minimum (t csl ) between consecutive instructions. if cs is low, the internal control logic is held in a reset status. 3.2 serial clock (clk) the serial clock is used to synchronize the communi- cation between a master device and the 93xx series device. opcodes, address and data bits are clocked in on the positive edge of clk. data bits are also clocked out on the positive edge of clk. clk can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (t ckh ) and clock low time (t ckl ). this gives the controlling master freedom in preparing opcode, address and data. clk is a ?don't care? if cs is low (device deselected). if cs is high, but the start condition has not been detected (di = 0 ), any number of clock cycles can be received by the device without changing its status (i.e., waiting for a start condition). clk cycles are not required during the self-timed write (i.e., auto erase/write) cycle. after detection of a start condition the specified number of clock cycles (respectively low-to-high transitions of clk) must be provided. these clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed. clk and di then become ?don't care? inputs waiting for a new start condition to be detected. 3.3 data in (di) data in (di) is used to clock in a start bit, opcode, address and data synchronously with the clk input. 3.4 data out (do) data out (do) is used in the read mode to output data synchronously with the clk input (t pd after the positive edge of clk). this pin also provides ready/busy status information during erase and write cycles. ready/busy status infor- mation is available on the do pin if cs is brought high after being low for minimum chip select low time (t csl ) and an erase or write operation has been initiated. the status signal is not available on do, if cs is held low during the entire erase or write cycle. in this case, do is in the high-z mode. if status is checked after the erase/write cycle, the data line will be high to indicate the device is ready. 3.5 organization (org) when the org pin is connected to v cc or logic hi, the (x16) memory organization is selected. when the org pin is tied to v ss or logic lo, the (x8) memory organization is selected. for proper operation, org must be tied to a valid logic level. 93xx46a devices are always x8 organization and 93xx46b devices are always x16 organization. name soic/pdip/ msop/ tssop/dfn sot-23 rotated soic function cs 1 5 3 chip select clk 2 4 4 serial clock di 3 3 5 data in do 4 1 6 data out vss 5 2 7 ground org/nc 6 ? 8 organization / 93xx46c no internal connection / 93xx46a/b nc 7 ? 1 no internal connection v cc 8 6 2 power supply note: after a programming cycle is complete, issuing a start bit and then taking cs low will clear the ready/busy status from do.
? 2005 microchip technology inc. ds21749f-page 13 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 4.0 packaging information 4.1 package marking information example: 6-lead sot-23 8-lead msop (150 mil) example: xxxxxxt ywwnnn 3l46bi 5281l7 xxnn 1el7 t/xxxnnn xxxxxxxx yyww 8-lead pdip 8-lead soic xxxxyyww xxxxxxxt nnn xxxx tyww 8-lead tssop nnn i/p 1l7 93lc46b 0528 example: example: sn 0528 93lc46bi 1l7 1l7 l46b i528 example: 3 e 3 e 8-lead 2x3 dfn example: 314 528 l7 xxx yww nn
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 14 ? 2005 microchip technology inc. part number 1st line marking codes tssop msop sot-23 dfn i temp. e temp. i temp. e temp. 93aa46a a46a 3a46at 1bnn ? 301 ? 93aa46b a46b 3a46bt 1lnn ? 311 ? 93aa46c a46c 3a46ct ? ? 321 ? 93lc46a l46a 3l46at 1enn 1fnn 304 305 93lc46b l46b 3l46bt 1pnn 1rnn 314 315 93lc46c l46c 3l46ct ? ? 324 325 93c46a c46a 3c46at 1hnn 1jnn 307 308 93c46b c46b 3c46bt 1tnn 1unn 317 318 93c46c c46c 3c46ct ? ? 327 328 note: t = temperature grade (i, e) nn = alphanumeric traceability code legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it wil l be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. * standard otp marking consists of microchip part number, year code, week code, and traceability code.
? 2005 microchip technology inc. ds21749f-page 15 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 8-lead plastic micro small outline package (ms) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not .0 3 7 ref f footprint (r e f e r e nc e ) e xc ee d .010" (0.254mm) p e r sid e . not e s: drawing no. c04-111 *controlling param e t e r mold draft angl e top mold draft angl e bottom foot angl e l e ad width l e ad thickn e ss c b .00 3 .009 .006 .012 dim e nsion limits ov e rall h e ight mold e d packag e thickn e ss mold e d packag e width ov e rall l e ngth foot l e ngth standoff ov e rall width numb e r of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .0 3 0 .19 3 typ. .0 33 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.2 3 0.40 8 millimeters* 0.65 bsc 0.85 3 .00 bsc 3 .00 bsc 0.60 4.90 bsc .04 3 .0 3 1 .0 3 7 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equival e nt: mo-187 0 - 8 5 5 - - 15 15 - - - -
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 16 ? 2005 microchip technology inc. 6-lead plastic small outline transistor (ot) (sot-23) 10 5 0 10 5 0 mold draft angl e bottom 10 5 0 10 5 0 mold draft angl e top 0.50 0.4 3 0. 3 5 .020 .017 .014 b l e ad width 0.20 0.15 0.09 .008 .006 .004 c l e ad thickn e ss 10 5 0 10 5 0 foot angl e 0.55 0.45 0. 3 5 .022 .018 .014 l foot l e ngth 3 .10 2.95 2.80 .122 .116 .110 d ov e rall l e ngth 1.75 1.6 3 1.50 .069 .064 .059 e1 mold e d packag e width 3 .00 2.80 2.60 .118 .110 .102 e ov e rall width 0.15 0.08 0.00 .006 .00 3 .000 a1 standoff 1. 3 0 1.10 0.90 .051 .04 3 .0 3 5 a2 mold e d packag e thickn e ss 1.45 1.18 0.90 .057 .046 .0 3 5 a ov e rall h e ight 1.90 .075 p1 outsid e l e ad pitch (basic) 0.95 .0 3 8 p pitch 6 6 n numb e r of pins max nom min max nom min dim e nsion limits millimeters inches* units 1 d b n e e1 l c a2 a a1 p1 e xc ee d .005" (0.127mm) p e r sid e . dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not not e s: jeita (form e rly eiaj) e quival e nt: sc-74a drawing no. c04-120 *controlling param e t e r
? 2005 microchip technology inc. ds21749f-page 17 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 18 ? 2005 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2005 microchip technology inc. ds21749f-page 19 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c 1 2 d n p b e e1 foot angle 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 20 ? 2005 microchip technology inc. 8-lead plastic dual flat no lead package (mc) 2x3x0.9 mm body (dfn) ? saw singulated exposed pad width exposed pad length contact length *controlling parameter contact width drawing no. c04-123 notes: exposed pad dimensions vary with paddle size. overall width e2 d2 l b e .016 .012 .008 .047 .055 .010 .118 bsc number of pins standoff contact thickness overall length overall height pitch p n units a a1 d a3 dimension limits 8 .000 .001 .008 ref. .079 bsc .031 .020 bsc min inches nom 0.40 0.25 3.00 bsc 0.30 .020 .071 .012 .064 0.20 1.20 1.39 0.50 0.30 1.80 1.62 0.02 0.80 2.00 bsc 0.20 ref. 0.50 bsc millimeters* .002 .039 0.00 min max nom 8 0.05 1.00 max 3. package may have one or more exposed tie bars at ends. 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. 0.90 .035 (not e 3) (not e 3) 4. jedec equivalent: mo-229 l e2 a3 a1 a top view d e exposed pad metal d2 bottom view 21 b p n (note 1) exposed tie bar pin 1 (note 2) id index area revised 05/24/04 -- -- -- --
? 2005 microchip technology inc. ds21749f-page 21 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c appendix a: revision history revision d corrections to section 1.0, electrical characteristics. section 4.1, 6-lead sot-23 package to ot. revision e added dfn package. revision f added notes throughout.
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 22 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21749f-page 23 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com in addition, there is a development systems information line which lists the latest versions of microchip?s development systems software products. this line also provides information on how customers can receive currently available upgrade kits. the development systems information line numbers are: 1-800-755-2345 ? united states and most of canada 1-480-792-7302 ? other international locations
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 24 ? 2005 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21749f 93aa46a/b/c, 93lc46a /b/c, 93c46a/b/c 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2005 microchip technology inc. ds21749f-page 25 93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . note: most products manufactured after ja nuary 2005 will have a matte tin (pb-free) finish. most products manufactured before january 2005 will have a finish of approximately 63% sn and 37% pb (sn/pb). please visit www.microchip.com/pbfree for the latest inform ation on pb-free conversion, in cluding conversion date codes. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. device: 93aa46a: 1k 1.8v microwire serial eeprom 93aa46b: 1k 1.8v microwire serial eeprom 93aa46c: 1k 1.8v microwire serial eeprom w/org 93lc46a: 1k 2.5v microwire serial eeprom 93lc46b: 1k 2.5v microwire serial eeprom 93lc46c: 1k 2.5v microwire serial eeprom w/org 93c46a: 1k 5.0v microwire serial eeprom 93c46b: 1k 5.0v microwire serial eeprom 93c46c: 1k 5.0v microwire serial eeprom w/org pinout: blank = standard pinout x = rotated pinout tape & reel: blank = standard packaging t = tape & reel temperature range: i = -40c to +85c e = -40c to +125c package: ms = plastic msop (micro small outline, 8-lead) ot = sot-23, 6-lead (tape & reel only) p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = tssop, 8-lead mc = 2x3 dfn, 8-lead lead finish: blank = pb-free ? matte tin (see note 1) g = pb-free ? matte tin only examples: a) 93aa46c-i/ms: 1k, 128x8 or 64x16 serial eeprom, msop package, 1.8v b) 93aa46b-i/ms: 1k, 64x16 serial eeprom, msop package, 1.8v c) 93aa46at-i/ot: 1k, 128x8 serial eeprom, sot-23 package, tape and reel, 1.8v d) 93aa46ct-i/ms: 1k, 128x8 or 16x16 serial eeprom, msop package, tape and reel, 1.8v a) 93lc46a-i/ms: 1k, 128x8 serial eeprom, msop package, 2.5v b) 93lc46bt-i/ot: 1k, 64x16 serial eeprom, sot-23 package, tape and reel, 2.5v c) 93lc46b-i/ms: 1k, 64x16 serial eeprom, msop package, 2.5v a) 93c46b-i/ms: 1k, 64x16 serial eeprom, msop package, 5.0v b) 93c46c-i/ms: 1k, 128x8 or 16x16 serial eeprom, msop package, 5.0v c) 93c46at-i/ot: 1k, 128x8 serial eeprom, sot-23 package, tape and reel, 5.0v part no. x /xx package temperature range device x lead finish x tape & reel x pinout
93aa46a/b/c, 93lc46a/b/c, 93c46a/b/c ds21749f-page 26 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21749f-page 27 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance and wiperlock are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
ds21749f-page 28 ? 2005 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta alpharetta, ga tel: 770-640-0034 fax: 770-640-0307 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 san jose mountain view, ca tel: 650-215-1444 fax: 650-961-0286 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8676-6200 fax: 86-28-8676-6599 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - qingdao tel: 86-532-502-7355 fax: 86-532-502-7205 asia/pacific india - bangalore tel: 91-80-2229-0061 fax: 91-80-2229-0062 india - new delhi tel: 91-11-5160-8631 fax: 91-11-5160-8632 japan - kanagawa tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel:011-604-646-8870 fax:011-604-646-5086 philippines - manila tel: 011-632-634-9065 fax: 011-632-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 taiwan - hsinchu tel: 886-3-572-9526 fax: 886-3-572-6459 europe austria - weis tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark - ballerup tel: 45-4450-2828 fax: 45-4485-2829 france - massy tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - ismaning tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 england - berkshire tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 04/20/05

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